1. Field of Invention
The present invention relates to integrated circuit designs. More particularly the use of alternative silicon chip geometries is disclosed to increase the ratio of the number of I/O pads to the effective number of logic gates while reducing the amount of unused silicon on an integrated circuit.
2. Description of Prior Art
As integrated circuits have become more complex, the speed and number of logic gates required on an integrated circuit chip has increased. This increase in the required number of logic gates has prompted the development of technology which enables smaller logic gates to be fabricated. With a decrease in the size of logic gates used on an integrated circuit, however, comes an increase in the amount of unused silicon on the integrated circuit. Although decreasing the overall die size of the integrated circuit to reduce the amount of unused silicon is possible to a certain extent, the pitch of required peripheral I/O pads often makes it impossible to reduce the die size to eliminate unused silicon completely.
FIG. 1A is a diagrammatic top view of an integrated circuit chip die 110 with a core area 114, areas of unused silicon 116, and peripheral I/O pads 118. FIG. 1A is intended to show the locations of core area 114, areas of unused silicon 116, and peripheral I/O pad 118, and should be understood to be a generic, off-scale representation of integrated circuit die 110. Core area 114 is comprised of logic gates (not shown). A logic gate is typically comprised of six to eight transistors, although some logic gates (AND gates and inverters, for example) may require fewer transistors. Peripheral I/O pads 118, located along the perimeter of integrated circuit chip die 110, are bonded to an external frame (not shown) in a later part of the semiconductor fabrication process to create a complete packaged integrated circuit chip.
Advances in semiconductor technology have made it possible to reduce the amount of silicon necessary to fabricate logic gates used in integrated circuits. For an integrated circuit chip of a fixed size, the decrease in the size of logic gates makes it possible to increase the density of logic gates on the integrated circuit chip. FIG. 1B is a diagrammatic top view of an integrated circuit chip die 140 with a core area 144, a large area of unused silicon 146, and peripheral I/O pads 148. It should be understood that although the illustration of integrated circuit chip die 140 in FIG. 1B with the large area of unused silicon 146 and the high density of peripheral I/O pads 148 is an exaggerated representation of an actual integrated circuit chip die, large areas of unused silicon 146 have indeed become more prevalent in integrated circuit chip dies 140 due to the fact that the decrease in size of logic gates (not shown) housed in core area 144 has enabled the density of logic gates to increase.
As semiconductor technology scales to smaller feature dimensions for integrated circuit chips, the available logic gate density increases with the square of the scaling factor. With the increase in the density of logic gates comes an increase in the required number of peripheral I/O pads 148. However, the pitch of peripheral I/O pads 148 scales much more slowly than the density of logic gates, and is constrained by assembly considerations, as for example wire bonding technology tolerances. As a result, the size of a silicon die, as for example integrated circuit die 140, is often determined by the number of peripheral I/O pads 148 necessary in a design rather than the area of silicon required for the logic circuitry itself. Such silicon dies are described as being pad limited.
Since the size of peripheral I/O pads 148 is constrained by packaging technology and assembly constraints as described above, the size of peripheral I/O pads 148 may only be reduced to a certain point. Hence, the size of peripheral I/O pads 148 cannot be decreased in order to enable a higher number of peripheral I/O pads 148 to be placed. Typically, the overall size of integrated circuit chip die 140 is increased in order to allow for a higher number of peripheral I/O pads 148 to be implemented. While the overall size of integrated circuit chip die 140 is increased to accommodate a higher number of peripheral I/O pads 148, core area 144 does not increase in size. The area of unused silicon 146, however, increases with the size of integrated circuit chip die 140.
FIG. 1C is a diagrammatic top view of a portion of an integrated circuit chip die 180 with I/O pads 188, I/O slots 190, and areas of unused silicon 184. FIG. 1C is intended to further illustrate why the size of integrated circuit chip die 180 may not simply be decreased to reduce the areas of unused silicon 184. As discussed above with reference to FIG. 1B, the size of peripheral I/O pads 188 may only be decreased to a certain extent due to technology and assembly considerations. In addition, integrated circuit chip die 180 has I/O slots 190 between areas of unused silicon 184 and peripheral I/O pads 188. I/O slots 190 contain transistors (not shown) which serve as amplifiers, buffers, etc.; the transistors in I/O slots 190 are typically larger than transistors which comprise logic gates (not shown) in the core area of integrated circuit chip die 180. Thus, the need for I/O slots 190 further prevents the possibility of shrinking the overall package size of integrated circuit chip die 180.
The area of a silicon die is a primary factor in determining the cost of fabricating an integrated circuit. As such, efforts have been made to reduce the amount of unused silicon on a die. In other words, efforts have been made to increase the available number of I/O pads while simultaneously reducing the size of the associated silicon die. One method which is used to increase the available number of I/O pads while reducing overall die size involves the use of a pad area array instead of the common peripheral ring of I/O pads. In this method, I/O pads are distributed across the area of a die rather than being confined to the periphery of the die. Although the use of a pad area array does reduce the amount of unused silicon on a die while allowing for more I/O pads to be incorporated into the die, implementing a pad area array requires significant modifications to the processes of fabricating and assembling integrated circuits. Any cost savings which may be gained from reducing the amount of silicon required on a die are most likely lost in the fabrication process.
The development of a method which reduces the amount of unused silicon on a die or a wafer, without significantly altering existing integrated circuit fabrication and assembly techniques, would reduce the overall cost associated with the semiconductor fabrication process.